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HD6475328-CP10 Datasheet, PDF (213/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)
10.6 Synchronization of Free-Running Timers 1 to 3
10.6.1 Synchronization after a Reset
The three free-running timer channels are synchronized at a reset and remained synchronized
until:
• the clock source is changed;
• FRC contents are rewritten; or
• an FRC is cleared.
After a reset, each free-running counter operates on the ø/4 internal clock source.
10.6.2 Synchronization by Writing to FRCs
When synchronization among free-running timers 1 to 3 is lost, it can be restored by writing to the
free-running counters.
Synchronization on Internal Clock Source: When an internal clock is selected, free-running
timers 1 to 3 can be synchronized by writing data to their free-running counters as indicated in
table 10-4.
Table 10-4 Synchronization by Writing to FRCs
Clock Source Write Interval
ø/4
4n + 1 (states)
ø/8
8n + 1 (states)
ø/32
32n + 1 (states)
m, n: Arbitrary integers
Write Data
m
(FRC1)
m + n (FRC2)
m + 2n (FRC3)
After writing these data, synchronization can be checked by reading the three free-running
counters at the same interval as the write interval. If the read data have the same relative
differences as the write data, the three free-running timers are synchronized.
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