HD6475328-CP10 Datasheet, PDF (447/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

ZTAT Versions
P10 / ø*
RES
Internal reset signal
External memory access
T1
T2
T3
A7 to A0
P57 /A15 to P50to A8
R/W
AS, RD and DS (read)
H’00
High impedance
WR and DS (write)
D7 to D0 (write)
I/O ports
High impedance
High impedance
* _{The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,}
but a clock output pin if the DDR bit is 1.
Figure E-3 Reset during Memory Access (Mode 2)
438