HD6475328-CP10 Datasheet, PDF (251/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

13.1.2 Block Diagram
Figure 13-1 is a block diagram of the watchdog timer.
NMI
(Watchdog timer mode)
Interrupt
signals
IRQ 0
(Interval timer mode)
Interrupt
control
Overflow
TCNT
TCSR
Clock _Clock
select
TCNT:Timer Counter
TCSR:Timer Control/Status Register
Read/
write
control
Internal data bus
Internal clock source
Øø//22
Øø//3322
Ø_ø/_/6₆4₄
Ø_ø/_/1₁2₂8₈
Ø_ø/_/2₂5₅6₆
Øø5/15212
Øø2/0240848
Øø4/0490696
Figure 13-1 Block Diagram of Timer Counter
13.1.3 Register Configuration
Table 13-1 lists information on the watchdog timer registers.
Table 13-1 Register Configuration
Initial
Addresses
Name
Abbreviation R/W Value Write
Read
Timer control/status register TCSR
R/(W)* H'18
H'FFED H'FFEC
Timer counter
TCNT
R/W H'00
H'FFED H'FFED
* Software can write a 0 to clear the status flag bits, but cannot write 1.
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