HD6475328-CP10 Datasheet, PDF (67/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Table 3-8 Effective Address Calculation (cont)
No. Addressing Mode Effective Address Calculation Effective Address
5
Absolute address —
23
15
0
@aa:8
H'00
BR
0000Sz101
EA extension data
@aa:16
—
0001Sz101
23
15
0
DP EA extension data
6
Immediate
—
#xx:8
00000100
Operand is 1-byte EA
extension data.
#xx:16
—
00001100
Operand is 2-byte EA
extension data.
7
PC-relative
8 Bits
disp:8
15
0
No EA code
PC
Specified in OP code
15
0
Displacement with
sign extension
23
15
0
CP ^*1
Result
⊕
disp:16
16 Bits
No EA code
15
0
Specified in OP code
PC
15
0
Displacement
23
15
0
CP ^*1
Result
⊕
Notes: * 1 The page register is ignored in minimum mode.
* 2 The page register used in addressing modes 2, 3, and 4 depends on the general register :
DP for R0, R1, R2, or R3; EP for R4 or R5; TP for R6 or R7.
* 3 Decrement by –1 for a byte operand, and by –2 for a word operand.
* 4 The pre-decrement or post-increment is always ±2 when R7 is specified, even if the
operand is byte size.
* 5 The drawing below shows what happens when the @-SP and @ SP+ addressing
modes are used to save and restore the stack pointer.
48