HD6475328-CP10 Datasheet, PDF (116/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Section 5 Interrupt Controller
5.1 Overview
The interrupt controller decides which interrupts to accept, and how to deal with multiple
interrupts. It also decides whether an interrupt should be served by the CPU or by the data
transfer controller (DTC). This section explains the features of the interrupt controller, describes
its internal structure and control registers, and details the handling of interrupts.
For detailed information on the data transfer controller, see section 6, “Data Transfer Controller.”
5.1.1 Features
Three main features of the interrupt controller are:
• Interrupt priorities are user-programmable.
User programs can set priority levels from 7 (high) to 0 (low) in four interrupt priority (IPR)
registers for IRQ0, IRQ1, and each of the on-chip supporting modules—for every interrupt, that
is, except the nonmaskable interrupt (NMI). NMI has the highest priority level (8) and is
normally always accepted. An interrupt with priority level 0 is always masked.
• Multiple interrupts on the same level are served in a default priority order.
Lower-priority interrupts remain pending until higher-priority interrupts have been handled.
• For most interrupts, software can select whether to have the interrupt served by the CPU or the
on-chip data transfer controller (DTC).
User programs can make this selection by setting and clearing bits in four data transfer enable
(DTE) registers. The data transfer controller can be started by any interrupts except NMI, the
error interrupt (ERI) from the on-chip serial communication interface, and the overflow
interrupts (FOVI and OVI) from the on-chip timers.
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