HD6475328-CP10 Datasheet, PDF (279/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an
overrun error occurs, however, the RSR contents are not transferred to the RDR.
If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1.
To clear a receive-error flag (ORER, FER, or PER), software must read the SSR, then write a 0
in the flag bit.
Table 14-8 Receive Errors
Name
Overrun error
Framing error
Parity error
Abbreviation
ORER
FER
PER
Description
Reception of the next frame ends while the RDRF bit is still
set to 1.
The RSR contents are not transferred to the RDR.
A stop bit is 0.
The RSR contents are transferred to the RDR.
The parity of a frame does not match the value selected by the bit
in the SMR.
The RSR contents are transferred to the RDR.
14.3.3 Synchronous Mode
The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is
synchronized with a serial clock pulse.
Continuous data transfer is enabled by the double buffering employed in both the transmit and
receive sections of the SCI. Full duplex communication is possible because the transmit and
receive sections are independent.
1. Data Format: Figure 14-4 shows the communication format used in the synchronous mode.
The data length is 8 bits for both the transmit and receive directions. The least significant bit
(LSB) is sent and received first. Each bit of transmit data is output from the falling edge of the
serial clock pulse to the next falling edge. Received bits are latched on the rising edge of the
serial clock pulse.
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