HD6475328-CP10 Datasheet, PDF (142/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Table 6-6 Number of States before Interrupt Service
Number of States
No. Reason for Wait
Minimum Mode
Maximum Mode
1 Interrupt priority decision and comparison with
2 states
mask level in CPU status register
2 Maximum number of Instruction is in on-chip
38
states to completion memory
(LDM instruction specifying all registers)
of current instruction Instruction is in external 74 + 16m
memory
(LDM instruction specifying all registers)
3 Saving of PC and SR Stack is in on-chip RAM 16
21
or PC, CP, and SR
and instruction prefetch Stack is in external memory 28 + 6m
41 + 10m
m: Number of wait states inserted in external memory access
6.4 Procedure for Using the DTC
A program that uses the DTC to transfer data must do the following:
1. Set the appropriate DTMR, DTSR, DTDR, and DTCR register information in the memory
location indicated in the DTC vector table.
2. Set the data transfer enable bit of the pertinent interrupt to “1,” and set the priority of the
interrupt source (in the interrupt priority register) and the interrupt mask level (in the CPU
status register) so that the interrupt can be accepted.
3. Set the interrupt enable bit in the control register for the interrupt source. (For IRQ0 and IRQ1,
the control register is the port 1 control register, P1CR.)
Following these preparations, the DTC will be started each time the interrupt occurs. When the
number of bytes or words designated by the DTCR value have been transferred, after transferring
the last byte or word, the DTC generates a CPU interrupt.
The user-coded interrupt-handling routine must take action to prepare for or disable further DTC
data transfer: by readjusting the data transfer count, for example, or clearing the interrupt enable
bit. If no action is taken, the next interrupt of the same type will start the DTC with an initial data
transfer count of 65,536.
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