HD6475328-CP10 Datasheet, PDF (140/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Table 6-4 Addresses of DTC Vectors (cont)
Interrupt
8-Bit
timer
Serial
communication
interface
A/D converter
CMIA
CMIB
OVI
ERI
RXI
TXI
ADI
Address of DTC Vector
Minimum Mode Maximum Mode
H'00A0 - H'00A1 H'0140 - H'0143
H'00A2 - H'00A3 H'0144 - H'0147
—
—
—
—
H'00AA - H'00AB H'0154 - H'0157
H'00AC - H'00AD H'0158 - H'015B
H'00B0 - H'00B1 H'0160 - H'0163
6.3.3 Location of Register Information in Memory
For each interrupt, the DTC control register information is stored in four consecutive words in
memory in the order shown in figure 6-5.
DTC vector table
RAM
DTMR
Mode register
TA + 2
DTSR
Source address register
TA
TA + 4
DTDR
Destination address register
TA + 6
DTCR
8 Bits 8 Bits
Count register
Figure 6-5 Order of Register Information
6.3.4 Length of Data Transfer Cycle
Table 6-5 lists the number of states required per data transfer, assuming that the DTC control
register information is stored in on-chip RAM. This is the number of states required for loading
and saving the DTC control registers and transferring one byte or word of data. Two cases are
considered: a transfer between on-chip RAM and a register belonging to an I/O port or on-chip
supporting module (i.e., a register in the register field from addresses H'FF80 to H'FFFF); and a
transfer between such a register and external RAM.
122