HD6475328-CP10 Datasheet, PDF (290/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

15.2 Register Descriptions
15.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE7
Bit
ADDRn H
Initial value
Read/Write
7
6
5
4
3
AD9
AD8
AD7
AD6
AD5
0
0
0
0
0
R
R
R
R
R
Bit
7
6
5
4
3
ADDRn H
AD1
AD0
—
—
—
Initial value
0
0
0
0
0
Read/Write
R
R
R
R
R
2
1
0
AD4
AD3
AD2
0
0
0
R
R
R
(n = A to D)
2
1
0
—
—
—
0
0
0
R
R
R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
Each result consist of 10 bits. The first 8 bits are stored in the upper byte of the data register
corresponding to the selected channel. The last two bits are stored in the lower data register byte.
Each data register is assigned to two analog input channels as indicated in table 15-3.
The A/D data registers are always readable by the CPU. The upper byte can be read directly. The
lower byte is read via a temporary register. See section 15-3, “CPU Interface” for details.
The unused bits (bits 5 to 0) of the lower data register byte are always read as 0.
The A/D data registers are initialized to H'0000 at a reset and in the standby modes.
Table 15-3 Assignment of Data Registers to Analog Input Channels
Analog Input Channel
Group 0 Group 1
AN0
AN4
AN1
AN5
AN2
AN6
AN3
AN7
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
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