HD6475328-CP10 Datasheet, PDF (291/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

15.2.2 A/D Control/Status Register (ADCSR)—H'FFE8
Bit
Initial value
Read/Write
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
* Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
The ADCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF
0
1
Description
This bit is cleared from 1 to 0 when:
(Initial value)
1. The chip is reset or placed in a standby mode.
2. The CPU reads the ADF bit, then writes a “0” in this bit.
3. An A/D interrupt is served by the data transfer controller (DTC).
This bit is set to 1 at the following times:
1. Single mode: when one A/D conversion is completed.
2. Scan mode: when inputs on all selected channels have been converted.
Bit 6—A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt
(ADI) when A/D conversion is completed.
Bit 6
ADIE
0
1
Description
The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
(Initial value)
277