HD6475328-CP10 Datasheet, PDF (252/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

13.2 Register Descriptions
13.2.1 Timer Counter TCNT—H'FFED
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
The watchdog timer counter (TCNT) is a readable/writable* 8-bit up-counter. When the timer
enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts
counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in
the TCSR. When the count overflows (changes from H'FF to H'00), an overflow flag (OVF) in the
TCSR is set to 1.
The watchdog timer counter is initialized to H'00 at a reset and when the TME bit is cleared to 0.
* TCNT is write-protected by a password. See section 13.2.3, “Notes on Register Access” for details.
13.2.2 Timer Control/Status Register (TCSR)—H'FFEC (Read), H'FFED (Write)
Bit
7
6
5
4
OVF WT/IT TME
—
Initial value
0
0
0
1
Read/Write R/(W)^*1 R/W R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W R/W R/W
The watchdog timer control/status register (TCSR) is an 8-bit readable/writable^*2 register that
selects the timer mode and clock source and performs other functions.
Bits 7 to 5 are initialized to 0 at a reset and in the standby modes. Bits 2 to 0 are initialized to 0 at
a reset, but retain their values in the standby modes.
*1 Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1.
*2 The TCSR is write-protected by a password. See section 13.2.3, “Notes on Register Access”
for details.
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