HD6475328-CP10 Datasheet, PDF (78/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

3.5.8 System Control Instructions
Table 3-16 describes the 12 system control instructions.
Table 3-16 System Control Instructions
Instruction
System TRAPA
control
TRAP/VS
RTE
LINK
UNLK
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Size
—
—
—
—
—
—
B/W*
B/W*
B/W*
B/W*
B/W*
—
Function
Generates a trap exception with a specified vector number.
Generates a trap exception if the V bit is set to “1” when
the instruction is executed.
Returns from an exception-handling routine.
FP → @–SP; SP → FP; SP + #IMM → SP
Creates a stack frame.
FP → SP; @SP+ → FP
Deallocates a stack frame created by the LINK instruction.
Causes a transition to the power-down state.
(EAs) → CR
Moves immediate data or general register or memory
contents to a specified control register.
CR → (EAd)
Moves control register data to a specified general register
or memory location.
CR ∧ #IMM → CR
Logically ANDs a control register with immediate data.
CR ∨ #IMM → CR
Logically ORs a control register with immediate data.
CR ⊕ #IMM → CR
Logically exclusive-ORs a control register with immediate
data.
PC + 1 → PC
No operation. Only increments the program counter.
* The size depends on the control register.
When using the LDC and STC instructions to stack and unstack the BR, CCR, TP, DP, and EP
control registers in the H8/500 family, note the following point.
H8/500 hardware does not permit byte access to the stack. If the LDC.B or STC.B assembler
mnemonic is coded with the @R7 + (@SP+) or @–R7 (@–SP) addressing mode, the stack-
pointer addressing mode takes precedence and hardware automatically performs word access.
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