HD6475328-CP10 Datasheet, PDF (54/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

3.2.2 Control Registers
The CPU control registers (CR) include a 16-bit program counter (PC), a 16-bit status register
(SR), four 8-bit page registers, and one 8-bit base register (BR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute.
Status Register (SR): This 16-bit register contains internal status information. The lower half of
the status register is referred to as the condition code register (CCR): it can be accessed as a
separate condition code byte.
CCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T — — — — I2 I1 I0 — — — — N Z V C
Bit 15—Trace (T): When this bit is set to “1,” the CPU operates in trace mode and generates a
trace exception after every instruction. See section 4.4, “Trace” for a description of the trace
exception-handling sequence.
When the value of this bit is “0,” instructions are executed in normal continuous sequence. This
bit is cleared to “0” at a reset.
Bits 14 to 11—Reserved: These bits cannot be modified and are always read as “0.”
Bits 10 to 8—Interrupt Mask (I2, I1, I0): These bits indicate the interrupt request mask level
(0 to 7). As shown in table 3-1, an interrupt request is not accepted unless it has a higher level
than the value of the mask. A nonmaskable interrupt (NMI), which has level 8, is accepted at any
mask level. After an interrupt is accepted, I2, I1, and I0 are changed to the level of the interrupt.
Table 3-2 indicates the values of the I bits after an interrupt is accepted.
A reset sets all three of bits (I2, I1, and I0) to “1,” masking all interrupts except NMI.
35