MC68HC11E0CFNE2 Datasheet, PDF (99/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Port B
6.3 Port B
In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test
modes, port B pins are high-order address outputs.
Address: $1004
Bit 7
6
5
4
3
2
1
Single-chip or bootstrap modes:
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Write:
Reset: 0
0
Expanded or special test modes:
Read:
ADDR15 ADDR14
Write:
Reset: 0
0
0
ADDR13
0
0
ADDR12
0
0
ADDR11
0
0
ADDR10
0
0
ADDR9
0
Figure 6-3. Port B Data Register (PORTB)
Bit 0
PB0
0
ADDR8
0
6.4 Port C
In single-chip and bootstrap modes, port C pins reset to high-impedance inputs. (DDRC bits are set to 0.)
In expanded and special test modes, port C pins are multiplexed address/data bus and the port C register
address is treated as an external memory location.
Address: $1003
Bit 7
6
5
4
3
2
1
Single-chip or bootstrap modes:
Read:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
Write:
Reset:
Expanded or special test modes:
Read: _ADDR7
Write: ^DATA7
ADDR6
DATA6
Reset:
Indeterminate after reset
ADDR5
DATA5
ADDR4
DATA4
ADDR3
DATA3
Indeterminate after reset
ADDR2
DATA2
ADDR1
DATA1
Figure 6-4. Port C Data Register (PORTC)
Bit 0
PC0
ADDR0
DATA0
Address: $1005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
Indeterminate after reset
PCL1
PCL0
Figure 6-5. Port C Latched Register (PORTCL)
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
99