MC68HC11E0CFNE2 Datasheet, PDF (100/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Parallel Input/Output (I/O) Ports
PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin,
port C data is latched into the PORTCL register. Reads of this register return the last value latched into
PORTCL and clear STAF flag (following a read of PIOC with STAF set).
Address:
Read:
Write:
Reset:
$1007
Bit 7
6
5
4
3
2
1
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1
0
0
0
0
0
0
0
Figure 6-6. Port C Data Direction Register (DDRC)
Bit 0
DDRC0
0
DDRC[7:0] — Port C Data Direction Bits
In the 3-state variation of output handshake mode, clear the corresponding DDRC bits. Refer to Figure
10-13. 3-State Variation of Output Handshake Timing Diagram (STRA Enables Output Buffer).
0 = Input
1 = Output
6.5 Port D
In all modes, port D bits [5:0] can be used either for general-purpose I/O or with the serial communications
interface (SCI) and serial peripheral interface (SPI) subsystems. During reset, port D pins PD[5:0] are
configured as high-impedance inputs (DDRD bits cleared).
Address: $1008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
Write:
0
PD5
PD4
PD3
PD2
PD1
PD0
Reset: —
—
I
I
I
I
I
I
Alternate Function: —
—
PD5
PD4
PD3
PD2
PD1
PD0
SS
SCK
MOSI
MISO
Tx
RxD
I = Indeterminate after reset
Figure 6-7. Port D Data Register (PORTD)
Address:
Read:
Write:
Reset:
$1009
Bit 7
6
5
4
3
2
1
DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
= Unimplemented
Figure 6-8. Port D Data Direction Register (DDRD)
Bit 0
DDRD0
0
Bits [7:6] — Unimplemented
Always read 0
DDRD[5:0] — Port D Data Direction Bits
When DDRD bit 5 is 1 and MSTR = 1 in SPCR, PD5/SS is a general-purpose output and mode fault
logic is disabled.
0 = Input
1 = Output
M68HC11E Family Data Sheet, Rev. 5.1
100
Freescale Semiconductor