MC68HC11E0CFNE2 Datasheet, PDF (131/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Input Capture
The control and status bits that implement the input capture functions are contained in:
• Pulse accumulator control register (PACTL)
• Timer control 2 register (TCTL2)
• Timer interrupt mask 1 register (TMSK1)
• Timer interrupt flag 2 register (TFLG1)
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit
is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on
the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4.
9.3.1 Timer Control Register 2
Use the control bits of this register to program input capture functions to detect a particular edge polarity
on the corresponding timer input pin. Each of the input capture functions can be independently configured
to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture
function. The input capture functions operate independently of each other and can capture the same
TCNT value if the input edges are detected within the same timer count cycle.
Address:
Read:
Write:
Reset:
$1021
Bit 7
6
5
4
3
2
1
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B
0
0
0
0
0
0
0
Figure 9-3. Timer Control Register 2 (TCTL2)
Bit 0
EDG3A
0
EDGxB and EDGxA — Input Capture Edge Control Bits
There are four pairs of these bits. Each pair is cleared to 0 by reset and must be encoded to configure
the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set. Refer to Table 9-2 for timer control configuration.
Table 9-2. Timer Control Configuration
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
9.3.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred
into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2 clock so that the count value is
stable whenever a capture occurs. The timer input capture registers are not affected by reset. Input
capture values can be read from a pair of 8-bit read-only registers. A read of the high-order byte of an
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
131