MC68HC11E0CFNE2 Datasheet, PDF (146/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Timing Systems
9.7.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI input or the
accumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.
The counter is not affected by reset and can be read or written at any time. Counting is synchronized to
the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
Address: $1027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 9-26. Pulse Accumulator Count Register (PACNT)
9.7.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF, are located within timer registers
TMSK2 and TFLG2.
Address: $1024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOI
Write:
RTII
PAOVI
PAII
PR1
PR0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-27. Timer Interrupt Mask 2 Register (TMSK2)
Address: $1025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
Write:
RTIF PAOVF PAIF
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2)
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To clear
this status bit, write a 1 in the corresponding data bit position (bit 5) of the TFLG2 register. The PAOVI
control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation
and does not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are
inhibited, and the system operates in a polled mode, which requires that PAOVF be polled by user
software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware
interrupt request is generated each time PAOVF is set. Before leaving the interrupt service routine,
software must clear PAOVF by writing to the TFLG2 register.
M68HC11E Family Data Sheet, Rev. 5.1
146
Freescale Semiconductor