MC68HC11E0CFNE2 Datasheet, PDF (143/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Computer Operating Properly (COP) Watchdog Function
PEDGE — Pulse Accumulator Edge Control Bit
Refer to 9.7 Pulse Accumulator.
DDRA3 — Data Direction for Port A Bit 3
Refer to Chapter 6 Parallel Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare Bit
Refer to 9.7 Pulse Accumulator.
RTR[1:0] — RTI Interrupt Rate Select Bits
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by an E divided by 2¹³ rate clock that is compensated so it is independent of the timer prescaler.
These two control bits select an additional division factor. Refer to Table 9-5.
9.6 Computer Operating Properly (COP) Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially
related to the main timer system. The CR[1:0] bits in the OPTION register and the NOCOP bit in the
CONFIG register determine the status of the COP function. One additional register, COPRST, is used to
arm and clear the COP watchdog reset system. Refer to Chapter 5 Resets and Interrupts for a more
detailed discussion of the COP function.
9.7 Pulse Accumulator
The M68HC11 Family of MCUs has an 8-bit counter that can be configured to operate either as a simple
event counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL
register. Refer to the pulse accumulator block diagram, Figure 9-24. In the event counting mode, the 8-bit
counter is clocked to increasing values by an external pin. The maximum clocking rate for the external
event counting mode is the E clock divided by two. In gated time accumulation mode, a free-running
E-clock divide-by-64 signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer
to Table 9-6. The pulse accumulator counter can be read or written at any time.
Table 9-6. Pulse Accumulator Timing
Crystal
Frequency
4.0 MHz
8.0 MHz
12.0 MHz
E Clock
1 MHz
2 MHz
3 MHz
Cycle Time
1000 ns
500 ns
333 ns
E ÷ 64
64 µs
32 µs
21.33 µs
PACNT
Overflow
16.384 ms
8.192 ms
5.461 ms
Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as
described in the following paragraphs.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
143