MC68HC11E0CFNE2 Datasheet, PDF (163/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

10.12 MC68L11E9/E20 Peripheral Port Timing
MC68L11E9/E20 Peripheral Port Timing
Characteristic^{(1) (2)}
1.0 MHz
2.0 MHz
Symbol
Unit
Min Max Min Max
Frequency of operation
E-clock frequency
f_o
dc
1.0
dc
2.0
MHz
E-clock period
Peripheral data setup time
MCU read of ports A, C, D, and E
t_CYC
1000 —
500
—
ns
t_PDSU
100
—
100
—
ns
Peripheral data hold time
MCU read of ports A, C, D, and E
t_PDH
50
—
50
—
ns
Delay time, peripheral data write
t_PWD = 1/4 t_CYC+ 150 ns
MCU writes to port A
MCU writes to ports B, C, and D
t_PWD
—
250
—
250
ns
—
400
—
275
Port C input data setup time
Port C input data hold time
Delay time, E fall to STRB
t_DEB = 1/4 t_CYC+ 150 ns
Setup time, STRA asserted to E fall⁽³⁾
t_IS
60
—
60
—
ns
t_IH
100
—
100
—
ns
t_DEB
—
400
—
275
ns
t_AES
0
—
0
—
ns
Delay time, STRA asserted to port C data output valid
Hold time, STRA negated to port C data
3-state hold time
t_PCD
t_PCH
t_PCZ
—
100
—
100
ns
10
—
10
—
ns
—
150
—
150
ns
1. V_DD = 3.0 Vdc to 5.5 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec-
tively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
Figure 10-7. Port Read Timing Diagram
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
163