MC68HC11E0CFNE2 Datasheet, PDF (29/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Chapter 2
Operating Modes and On-Chip Memory
2.1 Introduction
This section contains information about the operating modes and the on-chip memory for M68HC11
E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E series.
Differences are noted where necessary.
2.2 Operating Modes
The values of the mode select inputs MODB and MODA during reset determine the operating mode.
Single-chip and expanded multiplexed are the normal modes.
• In single-chip mode only on-chip memory is available.
• Expanded mode, however, allows access to external memory.
Each of the two normal modes is paired with a special mode:
• Bootstrap, a variation of the single-chip mode, is a special mode that executes a bootloader
program in an internal bootstrap ROM.
• Test is a special mode that allows privileged access to internal resources.
2.2.1 Single-Chip Mode
In single-chip mode, ports B and C and strobe pins A (STRA) and B (STRB) are available for
general-purpose parallel input/output (I/O). In this mode, all software needed to control the MCU is
contained in internal resources. If present, read-only memory (ROM) and/or erasable, programmable
read-only memory (EPROM) will always be enabled out of reset, ensuring that the reset and interrupt
vectors will be available at locations $FFC0–$FFFF.
NOTE
For the MC68HC811E2, the vector locations are the same; however, they
are contained in the 2048-byte EEPROM array.
2.2.2 Expanded Mode
In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes:
• The same on-chip memory addresses used for single-chip mode
• Addresses for external peripherals and memory devices
The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W
(read/write). R/W and AS allow the low-order address and the 8-bit data bus to be multiplexed on the
same pins. During the first half of each bus cycle address information is present. During the second half
of each bus cycle the pins become the bidirectional data bus. AS is an active-high latch enable signal for
an external address latch. Address information is allowed through the transparent latch while AS is high
and is latched when AS drives low.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
29