MC68HC11E0CFNE2 Datasheet, PDF(63/242 Page) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

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MC68HC11E0CFNE2 Datasheet, PDF (63/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

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A/D Control/Status Register

When this control bit is clear, the four requested conversions are performed once to fill the four result

registers. When this control bit is set, conversions are performed continuously with the result registers

updated as data becomes available.

MULT â Multiple Channel/Single Channel Control Bit

When this bit is clear, the A/D converter system is configured to perform four consecutive conversions

on the single channel specified by the four channel select bits CD:CA (bits [3:0] of the ADCTL register).

When this bit is set, the A/D system is configured to perform a conversion on each of four channels

where each result register corresponds to one channel.

NOTE

When the multiple-channel continuous scan mode is used, extra care is

needed in the design of circuitry driving the A/D inputs. The charge on the

capacitive DAC array before the sample time is related to the voltage on the

previously converted channel. A charge share situation exists between the

internal DAC capacitance and the external circuit capacitance. Although

the amount of charge involved is small, the rate at which it is repeated is

every 64 Âµs for an E clock of 2 MHz. The RC charging rate of the external

circuit must be balanced against this charge sharing effect to avoid errors

in accuracy. Refer to M68HC11 Reference Manual, Freescale document

order number M68HC11RM/AD, for further information.

CD:CA â Channel Selects D:A Bits

Refer to Table 3-2. When a multiple channel mode is selected (MULT = 1), the two least significant

channel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four

channels is to be converted.

Table 3-2. A/D Converter Channel Selection

Channel Select

Control Bits

CD:CC:CB:CA

0000

0001

0010

0011

0100

0101

0110

0111

10XX

1100

1101

1110

1111

Channel Signal

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Reserved

VRH(1)

VRL(1)

(VRH)/2(1)

Reserved(1)

1. Used for factory testing

Result in ADRx

if MULT = 1

ADR1

ADR2

ADR3

ADR4

ADR1

ADR2

ADR3

ADR4

â

ADR1

ADR2

ADR3

ADR4

M68HC11E Family Data Sheet, Rev. 5.1

Freescale Semiconductor

63

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