MC68HC11E0CFNE2 Datasheet, PDF (59/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Overview
3.2.3 Digital Control
All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the analog
input to be converted, ADCTL bits indicate conversion status and control whether single or continuous
conversions are performed. Finally, the ADCTL bits determine whether conversions are performed on
single or multiple channels.
3.2.4 Result Registers
Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can be accessed by the
processor in the CPU. The conversion complete flag (CCF) indicates when valid data is present in the
result registers. The result registers are written during a portion of the system clock cycle when reads do
not occur, so there is no conflict.
3.2.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock or an
internal RC oscillator for synchronization. When E-clock frequency is below 750 kHz, charge leakage in
the capacitor array can cause errors, and the internal oscillator should be used. When the RC clock is
used, additional errors can occur because the comparator is sensitive to the additional system clock
noise.
3.2.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can repeat continuously or stop after one iteration. The conversion complete flag (CCF) is set after the
fourth conversion in a sequence to show the availability of data in the result registers. Figure 3-3 shows
the timing of a typical sequence. Synchronization is referenced to the system E clock.
E CLOCK
12 E CYCLES
SAMPLE ANALOG INPUT
MSB
4
CYCLES
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB 2
2
2
2
2
2
2
2 CYC
CYC CYC CYC CYC CYC CYC CYC END
SUCCESSIVE APPROXIMATION SEQUENCE
CONVERT FIRST
CONVERT SECOND
CONVERT THIRD
CONVERT FOURTH
CHANNEL, UPDATE
CHANNEL, UPDATE
CHANNEL, UPDATE
CHANNEL, UPDATE
0
ADR1
32
ADR2
64
ADR3
96
ADR4
128 — E CYCLES
Figure 3-3. A/D Conversion Sequence
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
59