MC68HC11E0CFNE2 Datasheet, PDF (110/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Serial Communications Interface (SCI)
7.7.1 Serial Communications Data Register
SCDR is a parallel register that performs two functions:
• The receive data register when it is read
• The transmit data register when it is written
Reads access the receive data buffer and writes access the transmit data buffer. Receive and transmit
are double buffered.
Address: $102F
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
R7/T7
R6/T6
R5/T5 R4/T4 R3/T3 R2/T2
Indeterminate after reset
R1/T1
Figure 7-3. Serial Communications Data Register (SCDR)
Bit 0
R0/T0
7.7.2 Serial Communications Control Register 1
The SCCR1 register provides the control bits that determine word length and select the method used for
the wakeup feature.
Address: $102C
Bit 7
6
5
Read:
R8
T8
Write:
4
3
2
M
WAKE
1
Bit 0
Reset:
I
I
0
0
0
0
0
0
I = Indeterminate after reset
= Unimplemented
Figure 7-4. Serial Communications Control Register 1 (SCCR1)
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores the ninth bit in the transmit data character.
Bit 5 — Unimplemented
Always reads 0
M — Mode Bit (select character format)
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Bits [2:0] — Unimplemented
Always read 0
M68HC11E Family Data Sheet, Rev. 5.1
110
Freescale Semiconductor