MC68HC11E0CFNE2 Datasheet, PDF (139/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Output Compare
9.4.9 Timer Interrupt Mask 2 Register
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer prescaler
control bits are included in this register.
Address: $1024
Bit 7
6
5
4
3
Read:
TOI
Write:
RTII
PAOVI
PAII
Reset: 0
0
0
0
0
= Unimplemented
2
1
Bit 0
PR1
PR0
0
0
0
Figure 9-19. Timer Interrupt Mask 2 Register (TMSK2)
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
RTII — Real-Time Interrupt Enable Bit
Refer to 9.5 Real-Time Interrupt (RTI).
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 9.7.3 Pulse Accumulator Status and Interrupt Bits.
PAII — Pulse Accumulator Input Edge Interrupt Enable Bit
Refer to 9.7.3 Pulse Accumulator Status and Interrupt Bits.
Bits [3:2] — Unimplemented
Always read 0
PR[1:0] — Timer Prescaler Select Bits
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can be written
only once, and the write must be within 64 cycles after reset. Refer to Table 9-1 and Table 9-4 for
specific timing values.
Table 9-4. Timer Prescale
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2
enable the corresponding interrupt sources.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
139