MC68HC11E0CFNE2 Datasheet, PDF (46/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Operating Modes and On-Chip Memory
Table 2-4. RAM Mapping
RAM[3:0]
Address
0000
$0000–$0xFF
0001
$1000–$1xFF
0010
$2000–$2xFF
0011
$3000–$3xFF
0100
$4000–$4xFF
0101
$5000–$5xFF
0110
$6000–$6xFF
0111
$7000–$7xFF
1000
$8000–$8xFF
1001
$9000–$9xFF
1010
$A000–$AxFF
1011
$B000–$BxFF
1100
$C000–$CxFF
1101
$D000–$DxFF
1110
$E000–$ExFF
1111
$F000–$FxFF
Table 2-5. Register Mapping
REG[3:0]
Address
0000
$0000–$003F
0001
$1000–$103F
0010
$2000–$203F
0011
$3000–$303F
0100
$4000–$403F
0101
$5000–$503F
0110
$6000–$603F
0111
$7000–$703F
1000
$8000–$803F
1001
$9000–$903F
1010
$A000–$A03F
1011
$B000–$B03F
1100
$C000–$C03F
1101
$D000–$D03F
1110
$E000–$E03F
1111
$F000–$F03F
2.3.3.3 System Configuration Options Register
The 8-bit, special-purpose system configuration options register (OPTION) sets internal system
configuration options during initialization. The time protected control bits, IRQE, DLY, and CR[1:0], can
be written only once after a reset and then they become read-only. This minimizes the possibility of any
accidental changes to the system configuration.
Address: $1039
Bit 7
6
5
4
3
Read:
ADPU
CSEL
IRQE⁽¹⁾
DLY⁽¹⁾
CME
Write:
2
1
Bit 0
CR1⁽¹⁾
CR0⁽¹⁾
Reset: 0
0
0
1
0
0
0
0
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during
special modes.
= Unimplemented
Figure 2-13. System Configuration Options Register (OPTION)
ADPU — Analog-to-Digital Converter Power-Up Bit
Refer to Chapter 3 Analog-to-Digital (A/D) Converter.
CSEL — Clock Select Bit
Selects alternate clock source for on-chip EEPROM charge pump. Refer to 2.5.1 EEPROM and
CONFIG Programming and Erasure for more information on EEPROM use.
CSEL also selects the clock source for the A/D converter, a function discussed in Chapter 3
Analog-to-Digital (A/D) Converter.
M68HC11E Family Data Sheet, Rev. 5.1
46
Freescale Semiconductor