MC68HC11E0CFNE2 Datasheet, PDF (168/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Electrical Characteristics
10.15 Expansion Bus Timing Characteristics
Num
Characteristic⁽¹⁾
1.0 MHz
2.0 MHz 3.0 MHz
Symbol
Unit
Min Max Min Max Min Max
Frequency of operation (E-clock frequency)
1 Cycle time
f_o
t_CYC
dc 1.0 dc 2.0 dc 3.0 MHz
1000 — 500 — 333 — ns
2 Pulse width, E low⁽²⁾, PW_EL = 1/2 t_CYC–23 ns
PW_EL 477 — 227 — 146 — ns
3 Pulse width, E high⁽²⁾, PW_EH = 1/2 t_CYC–28 ns
4a E and AS rise time
PW_EH 472 — 222 — 141 — ns
t_r
— 20 — 20 — 20 ns
4b E and AS fall time
t_f
— 20 — 20 — 15 ns
9 Address hold time^{(2) (3)a}, t_AH = 1/8 t_CYC–29.5 ns
t_AH
95.5 — 33 — 26 — ns
Non-multiplexed address valid time to E rise
12
t_AV = PW_EL –(t_ASD + 80 ns)^{(2) (3)a}
17 Read data setup time
t_AV 281.5 — 94 — 54 — ns
t_DSR
30 — 30 — 30 — ns
18 Read data hold time, max = t_MAD
t_DHR
0 145.5 0 83 0 51 ns
19 Write data delay time, t_DDW = 1/8 t_CYC+ 65.5 ns^{(2) (3)a}
t_DDW
— 190.5 — 128
71 ns
21 Write data hold time, t_DHW = 1/8 t_CYC–29.5 ns^{(2) (3)a}
t_DHW 95.5 — 33 — 26 — ns
Multiplexed address valid time to E rise
22
t_AVM = PW_EL –(t_ASD + 90 ns)^{(2) (3)a}
Multiplexed address valid time to AS fall
24
t_ASL = PW_ASH –70 ns⁽²⁾
t_AVM 271.5 — 84 — 54 — ns
t_ASL
151 — 26 — 13 — ns
Multiplexed address hold time
25
t_AHL = 1/8 t_CYC–29.5 ns^{(2) (3)b}
26 Delay time, E to AS rise, t_ASD = 1/8 t_CYC–9.5 ns^{(2) (3)a}
27 Pulse width, AS high, PW_ASH = 1/4 t_CYC–29 ns⁽²⁾
t_AHL 95.5 — 33 — 31 — ns
t_ASD 115.5 — 53 — 31 — ns
PW_ASH 221 — 96 — 63 — ns
28 Delay time, AS to E rise, t_ASED = 1/8 t_CYC–9.5 ns^{(2) (3)b}
t_ASED 115.5 — 53 — 31 — ns
29
MPU address access time^(3)a
t_ACCA = t_CYC–(PW_EL–t_AVM) –t_DSR–t_f
35 MPU access time, t_ACCE = PW_EH –t_DSR
t_ACCA 744.5 — 307 — 196 — ns
t_ACCE
— 442 — 192
111 ns
Multiplexed address delay (Previous cycle MPU read)
36
t_MAD = t_ASD + 30 ns^{(2) (3)a}
t_MAD 145.5 — 83 — 51 — ns
1. V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless oth-
erwise noted
2. Formula only for dc to 2 MHz
3. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 t_CYCin the above formulas, where applicable:
(a) (1–dc) × 1/4 t_CYC
(b) dc × 1/4 t_CYC
Where:
dc is the decimal value of duty cycle percentage (high time)
M68HC11E Family Data Sheet, Rev. 5.1
168
Freescale Semiconductor