MC68HC11E0CFNE2 Datasheet, PDF (42/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Operating Modes and On-Chip Memory
0
0
0
1
Bootstrap
Special test
1
0
1
1
IRV(NE) — Internal Read Visibility (Not E) Bit
IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on
or off. In special test mode, IRVNE is reset to 1. In all other modes, IRVNE is reset to 0. For the
MC68HC811E2, this bit is IRV and only controls the internal read visibility function.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip. For the
MC68HC811E2, this bit has no meaning or effect in single-chip and bootstrap modes.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Mode
Single chip
Expanded
Bootstrap
Special test
IRVNE Out
of Reset
0
0
0
1
E Clock Out
of Reset
On
On
On
On
IRV Out
of Reset
Off
Off
Off
On
IRVNE
Affects Only
E
IRV
E
IRV
IRVNE Can
Be Written
Once
Once
Once
Once
PSEL[3:0] — Priority Select Bits
Refer to Chapter 5 Resets and Interrupts.
2.3.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are protected against
writes except under special circumstances. Table 2-2 lists registers that can be written only once after
reset or that must be written within the first 64 cycles after reset.
Table 2-2. Write Access Limited Registers
Operating Register
Mode Address
Register Name
SMOD = 0 $x024 Timer interrupt mask 2 (TMSK2)
$x035 Block protect register (BPROT)
$x039 System configuration options (OPTION)
$x03C
Highest priority I-bit interrupt
and miscellaneous (HPRIO)
$x03D RAM and I/O map register (INIT)
SMOD = 1 $x024 Timer interrupt mask 2 (TMSK2)
$x035 Block protect register (BPROT)
$x039 System configuration options (OPTION)
$x03C
Highest priority I-bit interrupt and
miscellaneous (HPRIO)
$x03D RAM and I/O map register (INIT)
Must be Written
in First 64 Cycles
Bits [1:0], once only
Clear bits, once only
Bits [5:4], bits [2:0], once only
Write
Anytime
Bits [7:2]
Set bits only
Bits [7:6], bit 3
See HPRIO description
See HPRIO description
Yes, once only
—
—
—
—
All, set or clear
All, set or clear
All, set or clear
See HPRIO description
See HPRIO description
—
All, set or clear
M68HC11E Family Data Sheet, Rev. 5.1
42
Freescale Semiconductor