MC68HC11E0CFNE2 Datasheet, PDF (97/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Chapter 6
Parallel Input/Output (I/O) Ports
6.1 Introduction
All M68HC11 E-series MCUs have five input/output (I/O) ports and up to 38 I/O lines, depending on the
operating mode. Refer to Table 6-1 for a summary of the ports and their shared functions.
Table 6-1. Input/Output Ports
Port
Port A
Port B
Port C
Port D
Port E
Input
Pins
3
—
—
—
8
Output
Pins
3
8
—
—
—
Bidirectional
Pins
2
—
8
6
—
Shared Functions
Timer
High-order address
Low-order address and data bus
Serial communications interface (SCI)
and serial peripheral interface (SPI)
Analog-to-digital (A/D) converter
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high-impedance inputs. I/O
pins configured as high-impedance inputs have port data that is indeterminate.
In port descriptions, an I indicates this condition. Port pins that are driven to a known logic level during
reset are shown with a value of either 1 or 0. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a U.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
97