MC68HC11E0CFNE2 Datasheet, PDF (124/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Serial Peripheral Interface (SPI)
MSTR — Master Mode Select Bit
It is customary to have an external pullup resistor on lines that are driven by open-drain devices.
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 8-2 and 8.4
Clock Phase and Polarity Controls.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure 8-2
and 8.4 Clock Phase and Polarity Controls.
SPR[1:0] — SPI Clock Rate Select Bits
These two bits select the SPI clock (SCK) rate when the device is configured as master. When the
device is configured as slave, these bits have no effect. Refer to Table 8-1.
Table 8-1. SPI Clock Rates
SPR[1:0]
Divide
E Clock By
00
2
01
4
10
16
11
32
Frequency at
E = 1 MHz
(Baud)
500 kHz
250 kHz
62.5 kHz
31.3 kHz
Frequency at
E = 2 MHz
(Baud)
1.0 MHz
500 kHz
125 kHz
62.5 kHz
Frequency at
E = 3 MHz (
Baud)
1.5 MHz
750 kHz
187.5 kHz
93.8 kHz
Frequency at
E = 4 MHz
(Baud)
2 MHz
1 MHz
250 kHz
125 kHz
8.7.2 Serial Peripheral Status Register
Address: $1029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
Write:
WCOL
MODF
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. Serial Peripheral Status Register (SPSR)
SPIF — SPI Interrupt Complete Flag
SPIF is set upon completion of data transfer between the processor and the external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit, read the
SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first, attempts to
write SPDR are inhibited.
WCOL — Write Collision Bit
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
of SPDR. Refer to 8.5.4 Slave Select and 8.6 SPI System Errors.
0 = No write collision
1 = Write collision
M68HC11E Family Data Sheet, Rev. 5.1
124
Freescale Semiconductor