MC68HC11E0CFNE2 Datasheet, PDF (137/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Output Compare
9.4.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byte
(LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit
state of the counter at the time of the MSB read cycle.
Register name: Timer Counter Register (High) Address: $100E
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Register name: Timer Counter Register (Low) Address: $100F
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-15. Timer Counter Register (TCNT)
9.4.6 Timer Control Register 1
The bits of this register specify the action taken as a result of a successful OCx compare.
Address: $1020
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 9-16. Timer Control Register 1 (TCTL1)
OM[2:5] — Output Mode Bits
OL[2:5] — Output Level Bits
These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5
functions only if the I4/O5 bit in the PACTL register is clear. Refer to Table 9-3 for the coding.
Table 9-3. Timer Output Compare Actions
OMx
0
0
1
1
OLx
Action Taken on Successful Compare
0 Timer disconnected from output pin logic
1 Toggle OCx output line
0 Clear OCx output line to 0
1 Set OCx output line to 1
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
137