MC68HC11E0CFNE2 Datasheet, PDF (157/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

10.10 MC68L11E9/E20 Control Timing
MC68L11E9/E20 Control Timing
Characteristic^{(1) (2)}
1.0 MHz
2.0 MHz
Symbol
Unit
Min Max Min Max
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup time
t_PCSU = 1/4 t_CYC+ 75 ns
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be pre-empted by internal reset)
f_o
t_CYC
f_XTAL
4 f_o
t_PCSU
dc 1.0 dc 2.0
1000 — 500 —
— 4.0 — 8.0
dc 4.0 dc 8.0
325 — 200 —
MHz
ns
MHz
MHz
ns
PW_RSTL
8
—
8
—
t_CYC
1
—
1
—
Mode programming setup time
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
PW_IRQ = t_CYC + 20 ns
Wait recovery startup time
Timer pulse width input capture pulse accumulator input
PW_TIM = t_CYC + 20 ns
t_MPS
t_MPH
2
—
2
—
10 — 10 —
PW_IRQ 1020 — 520 —
t_WRS
—
4
—
4
PW_TIM 1020 — 520 —
t_CYC
ns
ns
t_CYC
ns
1. V_DD = 3.0 Vdc to 5.5 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5
Resets and Interrupts for further detail.
PA[2:0]⁽¹⁾
PA[2:0]⁽²⁾
PA7^{(1) (3)}
PW_TIM
PA7^{(2) (3)}
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure 10-2. Timer Inputs
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
157