MC68HC11E0CFNE2 Datasheet, PDF (65/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
Features of the M68HC11 Family include:
• Central processor unit (CPU) architecture
• Data types
• Addressing modes
• Instruction set
• Special operations such as subroutine calls and interrupts
The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as
addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. There are no special
instructions for I/O that are separate from those used for memory. This architecture also allows accessing
an operand from an external memory location with no execution time penalty.
4.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed in the following paragraphs, are shown in Figure 4-1.
7
A
15
07
B
D
0 8-BIT ACCUMULATORS A & B
0 OR 16-BIT DOUBLE ACCUMULATOR D
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PC
7
0
SXH I NZVC
PROGRAM COUNTER
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
Figure 4-1. Programming Model
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
65