MC68HC11E0CFNE2 Datasheet, PDF (67/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

CPU Registers
At the end of the interrupt service routine, an return-from interrupt (RTI) instruction is executed. The RTI
instruction causes the saved registers to be pulled off the stack in reverse order. Program execution
resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often
used to preserve program context. For example, pushing accumulator A onto the stack when entering a
subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the
subroutine ensures that the contents of a register will be the same after returning from the subroutine as
it was before starting the subroutine.
JSR, JUMP TO SUBROUTINE
RTI, RETURN FROM INTERRUPT
MAIN PROGRAM
INTERRUPT ROUTINE
7 ^STACK 0
PC
DIRECT
$9D = JSR
dd
PC
$3B = RTI
SP
SP+1
CCR
RTN NEXT MAIN INSTR.
SP+2
ACCB
INDEXED, X
MAIN PROGRAM
PC $AD = JSR
ff
RTN NEXT MAIN INSTR.
INDEXED, Y
MAIN PROGRAM
PC $18 = PRE
$AD = JSR
RTN
ff
NEXT MAIN INSTR.
INDEXED, Y
MAIN PROGRAM
PC $BD = PRE
hh
RTN
ll
NEXT MAIN INSTR.
7 ^STACK 0
È SP–2
SP–1
RTN_H
SP
RTN_L
BSR, BRANCH TO SUBROUTINE
MAIN PROGRAM
7 ^STACK 0
SP+3
ACCA
SP+4
SP+5
SP+6
SP+7
SP+8
È SP+9
IX_H
IX_L
IY_H
IY_L
RTN_H
RTN_L
SWI, SOFTWARE INTERRUPT
MAIN PROGRAM
7 ^STACK 0
PC
$3F = SWI
È SP–9
SP–8
CCR
SP–7
ACCB
SP–6
ACCA
SP–5
WAI, WAIT FOR INTERRUPT
SP–4
MAIN PROGRAM
SP–3
PC $3E = WAI
SP–2
SP–1
SP
IX_H
IX_L
IY_H
IY_L
RTN_H
RTN_L
PC $8D = BSR
RTS, RETURN FROM
SUBROUTINE
MAIN PROGRAM
PC
$39 = RTS
È SP–2
SP–1
SP
RTN_H
RTN_L
7 ^STACK 0
SP
SP+1
È SP+2
RTN_H
RTN_L
LEGEND:
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
BE EXECUTED UPON RETURN FROM SUBROUTINE
RTN_H = MOST SIGNIFICANT BYTE OF RETURN ADDRESS
RTN_L = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
È = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
Figure 4-2. Stacking Operations
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
67