MC68HC11E0CFNE2 Datasheet, PDF (115/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

SCI Registers
SCR[2:0] — SCI Baud Rate Select Bits
Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to
Figure 7-8 and Figure 7-9.
The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] bits select an
additional binary submultiple (÷1, ÷2, ÷4, through ÷128) of this highest baud rate. The result of these
two dividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset
and can be changed at any time, although they should not be changed when any SCI transfer is in
progress.
Figure 7-8 and Figure 7-9 illustrate the SCI baud rate timing chain. The prescaler select bits determine
the highest baud rate. The rate select bits determine additional divide by two stages to arrive at the
receiver timing (RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16.
EXTAL
XTAL
OSCILLATOR
AND
CLOCK GENERATOR
(÷4)
E
AS
INTERNAL BUS CLOCK (PH2)
÷3
0:0
0:1
÷4
1:0
÷ 13
SCP[1:0]
1:1
SCR[2:0]
0:0:0
÷2
0:0:1
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
÷ 16
SCI
TRANSMIT
BAUD RATE
(1X)
÷2
1:1:1
SCI
RECEIVE
BAUD RATE
(16X)
Figure 7-8. SCI Baud Rate Generator Block Diagram
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
115