MC68HC11E0CFNE2 Datasheet, PDF (82/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Resets and Interrupts
5.2.5 System Configuration Options Register
Address: $1039
Bit 7
6
5
4
3
2
1
Read:
ADPU
CSEL
IRQE⁽¹⁾
DLY⁽¹⁾
CME
Write:
CR1⁽¹⁾
Reset: 0
0
0
1
0
0
0
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
= Unimplemented
Bit 0
CR0⁽¹⁾
0
Figure 5-2. System Configuration Options Register (OPTION)
ADPU — Analog-to-Digital Converter Power-Up Bit
Refer to Chapter 3 Analog-to-Digital (A/D) Converter.
CSEL — Clock Select Bit
Refer to Chapter 3 Analog-to-Digital (A/D) Converter.
IRQE — Configure IRQ for Edge-Sensitive-Only Operation Bit
0 = IRQ is configured for level-sensitive operation.
1 = IRQ is configured for edge-sensitive-only operation.
DLY — Enable Oscillator Startup Delay Bit
Refer to Chapter 2 Operating Modes and On-Chip Memory and Chapter 3 Analog-to-Digital (A/D)
Converter.
CME — Clock Monitor Enable Bit
This control bit can be read or written at any time and controls whether or not the internal clock monitor
circuit triggers a reset sequence when the system clock is slow or absent. When it is clear, the clock
monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. Reset clears the CME
bit.
0 = Clock monitor circuit disabled
1 = Slow or stopped clocks cause reset
Bit 2 — Unimplemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bit
The internal E clock is first divided by 2¹⁵ before it enters the COP watchdog system. These control
bits determine a scaling factor for the watchdog timer. See Table 5-1 for specific timeout settings.
M68HC11E Family Data Sheet, Rev. 5.1
82
Freescale Semiconductor