MC68HC11E0CFNE2 Datasheet, PDF (44/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

Operating Modes and On-Chip Memory
Address: $103F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EE3
EE2
EE1
EE0
NOSEC NOCOP
Write:
EEON
Resets:
Single chip: 1
1
1
1
U
U
1
1
Bootstrap: 1
1
1
1
U
U(L)
1
1
Expanded: U
U
U
U
1
U
1
U
Test: U
U
U
U
1
U(L)
1
0
= Unimplemented
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG)
EE[3:0] — EEPROM Mapping Bits
EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any
4-Kbyte boundary. See Table 2-3.
Table 2-3. EEPROM Mapping
EE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
EEPROM Location
$0800–$0FFF
$1800–$1FFF
$2800–$2FFF
$3800–$3FFF
$4800–$4FFF
$5800–$5FFF
$6800–$6FFF
$7800–$7FFF
$8800–$8FFF
$9800–$9FFF
$A800–$AFFF
$B800–$BFFF
$C800–$CFFF
$D800–$DFFF
$E800–$EFFF
$F800–$FFFF
M68HC11E Family Data Sheet, Rev. 5.1
44
Freescale Semiconductor