MC68HC11E0CFNE2 Datasheet, PDF (165/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

MC68L11E9/E20 Peripheral Port Timing
WRWITREITPEOPORRTTCCLL⁽¹¹⁾
EE
POPORRTTCC((OOUT) PRPEREVVIOIOUUSSPPOORRT DAATTAA
t_{tPPW WDD}
STRB (IN)
STRB (OUT)
STRA (IN)
STRA (IN)
NEW W DDAATTAA VVAALLIIDD
t_DDEEBB
“R_"RE_EA_AD_DY_Y”_"
tt_AA_EE_SS
tt_DDEEB
No^Nt^Oe^Ts^E: ^S:
1.^1.A^Af^ft^te^err^rr^ee^adaⁱⁿd^gin^PIg^OCPI^wO^ithC^Sw^TAit^Fh^seS^t TAF set
2.^2.F^Fiⁱg^guu^rr^ee^shs^oh^wo^{s r}w^iss^ingri^es^di^gn^eg^STe^Rd^Age^(EGS^AT⁼R¹A^{) a}(ⁿE^dG^higA^h =^tru1^e )^STa^Rn^Bd^(Ih^Ni^Vg^Bh ⁼tr¹u^).e STRB (INVB = 1).
PORT C OUTPUT HNDSHK TIM
Figure 10-12. Port C Output Handshake Timing Diagram
EE
PPOORRTTCC (OUUTT))
(D_DD_DR_R=₌1₁)
SSTTRRBB((OOUUTT))
RREEAADDPPOORRTTCCLL¹⁽¹⁾
tt_PPWWD
t_DEEBB
"“RREEAADDYY" ”
tt_DDEEBB
tt_AAEESS
S^ST^TR^RA^A (I^IN^N)
PPOORRTTCC (OUUTT))
(DDRR==00)
t_tPPCCDD
OOLLDDDDAATTAA
NE^NW^EWDA^DT^AA^TAVA^VL^AI^LD^ID
aa))SSTTRRAAAACCTITVIEVEBEBFEOFROERPEORPTOCRLTWCRLITWERITE
t^t_PP_CC_HH
tt_PCCZ
S^ST^TR^RA^A (I^IN^N)
t_tPPCCDD
PPOORRTTCC (OUUTT))
(DDRR==00)
bb) STTRRAAAACCTTIVIVEEAAFFTETRERPOPROTRCLTCWLRWITREITE
t_PCHH
NENWEWDDAATTAAVVAALLIDID
tt_PCCZZ
NOTES:
Note_1.s_A:_{fter reading PIOC with STAF set}
12₂.._{. F}AF_igifgute_ruerr_sehr_oe_wsahsd_roiin_swings_g P_erdiIsgO_einCSgTRwe_Aidt₍hg_EeGS_AST=AT_{1RF) aAsnd}e(_htE_{igGhAtrue=S1T)RBan(IdNVhBig=h1)t.rue STRB (INVB = 1).}
Figure 10-13. 3-State Variation of Output Handshake Timing Diagram
(STRA Enables Output Buffer)
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
165