MC68HC11E0CFNE2 Datasheet, PDF(147/242 Page) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

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MC68HC11E0CFNE2 Datasheet, PDF (147/242 Pages) Freescale Semiconductor, Inc – M68HC11 CPU, Power-saving stop and wait modes, Low-voltage devices available (3.0–5.5 Vdc)

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Pulse Accumulator

PAII and PAIF â Pulse Accumulator Input Edge Interrupt Enable Bit and Flag

The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1 pin.

To clear this status bit, write to the TFLG2 register with a 1 in the corresponding data bit position (bit

4). The PAII control bit allows configuring the pulse accumulator input edge detect for polled or

interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII is 0, pulse

accumulator input interrupts are inhibited, and the system operates in a polled mode. In this mode, the

PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII

control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the

interrupt service routine, software must clear PAIF by writing to the TFLG2 register.

M68HC11E Family Data Sheet, Rev. 5.1

Freescale Semiconductor

147

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