MC9S12C Datasheet, PDF (65/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.7.4 VREGEN
The VREGEN input mentioned in the VREG section is device internal, connected internally to V_DDR.
1.7.5 V_DD1, V_DD2, V_SS1, V_SS2
In the 80-pin QFP package versions, both internal V_DD and V_SS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (V_DD1, V_SS1 & V_DD2, V_SS2). V_DD1 and V_DD2 are connected together
internally. V_SS1 and V_SS2 are connected together internally. The extra pin pair enables systems using the
80-pin package to employ better supply routing and further decoupling.
1.7.6 Clock Reset Generator And VREG Interface
The low voltage reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset.
NOTE
If the voltage regulator is shut down by connecting V_DDR to ground then the
LVRF flag in the CRG flags register (CRGFLG) is undefined.
1.7.7 Analog-to-Digital Converter
In the 48- and 52-pin package versions, the V_RL pad is bonded internally to the V_SSA pin.
1.7.8 MODRR Register Port T And Port P Mapping
The MODRR register within the PIM allows for mapping of PWM channels to port T in the absence of
port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use
MODRR since this is intended to support PWM channel availability in low pin count packages. Note that
when mapping PWM channels to port T in an 80QFP option, the associated PWM channels are then
mapped to both port P and port T. .
1.7.9 Port AD Dependency On PIM And ATD Registers
The port AD pins interface to the PIM module. However, the port pin digital state can be read from either
the PORTAD register in the ATD register map or from the PTAD register in the PIM register map.
In order to read a digital pin value from PORTAD the corresponding ATDDIEN bit must be set and the
corresponding DDRDA bit cleared. If the corresponding ATDDIEN bit is cleared then the pin is configured
as an analog input and the PORTAD bit reads back as "1".
In order to read a digital pin value from PTAD, the corresponding DDRAD bit must be cleared, to
configure the pin as an input.
Furthermore in order to use a port AD pin as an analog input, the corresponding DDRAD bit must be
cleared to configure the pin as an input
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
65
Rev 01.23