MC9S12C Datasheet, PDF (272/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.5 Computer Operating Properly Watchdog (COP)
OSCCLK
WAIT(COPWAI),
STOP(PSTP,PCE),
COP enable
CR[2:0]
0:0:0
CR[2:0]
0:0:1
÷ 16384
÷4
0:1:0
÷4
0:1:1
gating condition
= Clock Gate
÷4
1:0:0
÷4
1:0:1
÷2
1:1:0
÷2
1:1:1
COP TIMEOUT
Figure 9-21. Clock Chain for COP
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. The COP is disabled out of reset. When the COP is being used, software is
responsible for keeping the COP from timing out. If the COP times out it is an indication that the software
is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 9.5.2,
“Computer Operating Properly Watchdog (COP) Reset).” The COP runs with a gated OSCCLK (see
Section Figure 9-21., “Clock Chain for COP”). Three control bits in the COPCTL register allow selection
of seven COP time-out periods.
When COP is enabled, the program must write 0x0055 and 0x00AA (in this order) to the ARMCOP
register during the selected time-out period. As soon as this is done, the COP time-out period is restarted.
If the program fails to do this and the COP times out, the part will reset. Also, if any value other than
0x0055 or 0x00AA is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in pseudo-stop mode.
9.4.6 Real-Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK (see Section Figure 9-22., “Clock Chain for RTI”). At the end of the RTI time-out period the
RTIF flag is set to 1 and a new RTI time-out period starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
272
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23