MC9S12C Datasheet, PDF (203/680 Pages) Motorola, Inc – 16-Bit Microcontroller

7.3.2.5
Chapter 7 Debug Module (DBGV1) Block Description
Debug Comparator C Extended Register (DBGCCX)
Module Base + 0x0025
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
PAGSEL
W
EXTCMP
Reset
0
0
0
0
0
0
0
0
Figure 7-9. Debug Comparator C Extended Register (DBGCCX)
Table 7-10. DBGCCX Field Descriptions
Field
7:6
PAGSEL
5:0
EXTCMP
Description
Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively).
Comparator C Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in Table 7-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing
comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and
B operate in BKP mode.
Table 7-11. PAGSEL Decoding⁽¹⁾
PAGSEL
Description
EXTCMP
Comment
00
Normal (64k)
Not used
No paged memory
01
PPAGE
EXTCMP[5:0] is compared to
PPAGE[7:0] / XAB[21:14] becomes
(256 — 16K pages)
address bits [21:16]⁽²⁾
address bits [21:14]¹
10⁽³⁾
DPAGE (reserved)
(256 — 4K pages)
EXTCMP[3:0] is compared to
address bits [19:16]
DPAGE / XAB[21:14] becomes address
bits [19:12]
11²
1. See Figure 7-10.
EPAGE (reserved)
(256 — 1K pages)
EXTCMP[1:0] is compared to
address bits [17:16]
EPAGE / XAB[21:14] becomes address
bits [17:10]
2. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00.
3. Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra
space.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
203
Rev 01.23