MC9S12C Datasheet, PDF (100/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.5.7 Port J Interrupt Enable Register (PIEJ)
Module Base + 0x002E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PIEJ7
PIEJ6
W
Reset
0
0
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-38. Port J Interrupt Enable Register (PIEJ)
Read: Anytime.
Write: Anytime.
Table 2-32. PIEJ Field Descriptions
Field
Description
7–6
PIEJ[7:6]
Interrupt Enable Port J — This register disables or enables on a per pin basis the edge sensitive external
interrupt associated with port J.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
2.3.2.5.8 Port J Interrupt Flag Register (PIFJ)
Module Base + 0x002F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PIFJ7
PIFJ6
W
Reset
0
0
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-39. Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Table 2-33. PIFJ Field Descriptions
Field
Description
7–6
PIFJ[7:6]
Interrupt Flags Port J — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in
the PIFJ register. Writing a “0” has no effect.
0 No active edge pending.
Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
100
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23