MC9S12C Datasheet, PDF (210/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 7 Debug Module (DBGV1) Block Description
PAGSEL
EXTCMP
DBGCXX 0
0
5
4
3
2
1
BIT 0
SEE NOTE 1
PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
SEE NOTE 2
NOTES:
1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state).
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
Figure 7-16. Comparators A and B Extended Comparison in BKP Mode
7.3.2.10 Debug Comparator A Register (DBGCA)
Module Base + 0x002B
Starting address location affected by INITRG register setting.
15
R
Bit 15
W
14
Bit 14
13
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
9
Bit 9
8
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 7-17. Debug Comparator A Register High (DBGCAH)
Module Base + 0x002C
Starting address location affected by INITRG register setting.
7
R
Bit 7
W
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 7-18. Debug Comparator A Register Low (DBGCAL)
Table 7-21. DBGCA Field Descriptions
Field
15:0
15:0
Description
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See Table 7-20.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
210
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23