MC9S12C Datasheet, PDF (243/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.3.2.12 Port Data Register (PORTAD)
The data port associated with the ATD is general purpose I/O. The port pins are shared with the analog
A/D inputs AN7–AN0.
Module Base + 0x000F
R
W
Reset
Pin
Function
7
PTAD7
1
AN7
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
1
1
1
1
1
AN6
AN5
AN4
AN3‘
AN2
= Unimplemented or Reserved
Figure 8-14. Port Data Register (PORTAD)
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general-purpose digital I/0.
Table 8-18. PORTAD Field Descriptions
1
PTAD1
1
AN1
0
PTAD0
1
AN0
Field
Description
7
PTAD[7:0]
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled
(IENx = 1) read returns the logic level on ANx pin (signal potentials not meeting V_IL or V_IH specifications will have
an indeterminate value)).
If the digital input buffers are disabled (IENx = 0), read returns a “1”.
Reset sets all PORTAD bits to “1”.
8.3.2.13 ATD Conversion Result Registers (ATDDRHx/ATDDRLx)
The A/D conversion results are stored in 8 read-only result registers ATDDRHx/ATDDRLx. The result
data is formatted in the result registers based on two criteria. First there is left and right justification; this
selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this
selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement
format and only exists in left justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime, no effect in normal modes
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
243
Rev 01.23