MC9S12C Datasheet, PDF (271/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
The sequence for clock quality check is shown in Figure 9-20.
Clock OK
CM fail
POR LVR
exit full stop
Clock Monitor Reset
num=0
check window
osc ok
no
?
yes
Enter SCM
yes
num=num+1
yes
num<50
no
?
no
SCM
active?
yes
SCME=1
no
?
num=50
SCM
active?
no
yes
Switch to OSCCLK
Exit SCM
Figure 9-20. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by self-clock mode
or clock monitor reset¹ handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The clock quality checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f_SCM) and an active VREG
during pseudo-stop mode or wait mode
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
271
Rev 01.23