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MC9S12C Datasheet, PDF (158/680 Pages) Motorola, Inc – 16-Bit Microcontroller | |||
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Chapter 5 Interrupt (INTV1) Block Description
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable
vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-
maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug
mode request, and three system reset vector requests. All interrupt related exception requests are managed
by the interrupt sub-block (INT).
5.1.1 Features
The INT includes these features:
⢠Provides two to 122 I-bit maskable interrupt vectors (0xFF00â0xFFF2)
⢠Provides one X-bit maskable interrupt vector (0xFFF4)
⢠Provides a non-maskable software interrupt (SWI) or background debug mode request vector
(0xFFF6)
⢠Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8)
⢠Provides three system reset vectors (0xFFFAâ0xFFFE) (reset, CMR, and COP)
⢠Determines the appropriate vector and drives it onto the address bus at the appropriate time
⢠Signals the CPU that interrupts are pending
⢠Provides control registers which allow testing of interrupts
⢠Provides additional input signals which prevents requests for servicing I and X interrupts
⢠Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ
is active, even if XIRQ is masked
⢠Provides asynchronous path for all I and X interrupts, (0xFF00â0xFFF4)
⢠(Optional) selects and stores the highest priority I interrupt based on the value written into the
HPRIO register
5.1.2 Modes of Operation
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that
follow.
⢠Normal operation
The INT operates the same in all normal modes of operation.
⢠Special operation
Interrupts may be tested in special modes through the use of the interrupt test registers.
⢠Emulation modes
The INT operates the same in emulation modes as in normal modes.
⢠Low power modes
See Section 5.4.1, âLow-Power Modes,â for details
158
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23
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