MC9S12C Datasheet, PDF (21/680 Pages) Motorola, Inc – 16-Bit Microcontroller

1.2
Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
Memory Map and Registers
1.2.1 Device Memory Map
Table 1-1 shows the device register map after reset. Figure 1-4 through Figure 1-8 illustrate the full device
memory map.
Table 1-1. Device Register Map Overview
Address
Module
Size
0x0000–0x0017 Core (ports A, B, E, modes, inits, test)
24
0x0018
Reserved
1
0x0019
Voltage regulator (VREG)
1
0x001A–0x001B Device ID register
2
0x001C–0x001F Core (MEMSIZ, IRQ, HPRIO)
4
0x0020–0x002F Core (DBG)
16
0x0030–0x0033 Core (PPAGE⁽¹⁾)
4
0x0034–0x003F Clock and reset generator (CRG)
12
0x0040–0x006F Standard timer module (TIM)
48
0x0070–0x007F Reserved
16
0x0080–0x009F Analog-to-digital converter (ATD)
32
0x00A0–0x00C7 Reserved
40
0x00C8–0x00CF Serial communications interface (SCI)
8
0x00D0–0x00D7 Reserved
8
0x00D8–0x00DF Serial peripheral interface (SPI)
8
0x00E0–0x00FF Pulse width modulator (PWM)
32
0x0100–0x010F Flash control register
16
0x0110–0x013F Reserved
48
0x0140–0x017F Scalable controller area network (MSCAN)⁽²⁾
64
0x0180–0x023F Reserved
192
0x0240–0x027F Port integration module (PIM)
64
0x0280–0x03FF Reserved
384
1. External memory paging is not supported on this device (Section 1.7.1, “PPAGE”).
2. Not available on MC9S12GC Family devices
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
21
Rev 01.23