MC9S12C Datasheet, PDF (262/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-5. PLLCTL Field Descriptions (continued)
Field
5
AUTO
4
ACQ
2
PRE
1
PCE
0
SCME
Description
Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low
bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime
except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1.
0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.
1 Automatic mode control is enabled and ACQ bit has no effect.
Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect.
0 Low bandwidth filter is selected.
1 High bandwidth filter is selected.
RTI Enable during Pseudo-Stop Bit — PRE enables the RTI during pseudo-stop mode. Write anytime.
0 RTI stops running during pseudo-stop mode.
1 RTI continues running during pseudo-stop mode.
Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers
will not initialize like in wait mode with RTIWAI bit set.
COP Enable during Pseudo-Stop Bit — PCE enables the COP during pseudo-stop mode. Write anytime.
0 COP stops running during pseudo-stop mode
1 COP continues running during pseudo-stop mode
Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers
will not initialize like in wait mode with COPWAI bit set.
Self-Clock Mode Enable Bit — Normal modes: Write once —Special modes: Write anytime — SCME can not
be cleared while operating in self-clock mode (SCM=1).
0 Detection of crystal clock failure causes clock monitor reset (see Section 9.5.1, “Clock Monitor Reset”).
1 Detection of crystal clock failure forces the MCU in self-clock mode (see Section 9.4.7.2, “Self-Clock Mode”).
9.3.2.8 CRG RTI Control Register (RTICTL)
This register selects the timeout period for the real-time interrupt.
Module Base + 0x0007
7
R
0
W
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-11. CRG RTI Control Register (RTICTL)
Read: anytime
Write: anytime
NOTE
A write to this register initializes the RTI counter.
1
RTR1
0
0
RTR0
0
262
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23