MC9S12C Datasheet, PDF (202/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.4 Debug Count Register (DBGCNT)
Module Base + 0x0024
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R TBF
0
CNT
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. Debug Count Register (DBGCNT)
Table 7-8. DBGCNT Field Descriptions
Field
7
TBF
5:0
CNT
Description
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was
last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit
is cleared when ARM in DBGC1 is written to a 1.
Count Value — The CNT bits indicate the number of valid data words stored in the trace buffer. Table 7-9 shows
the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls
over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The
DBGCNT register is cleared when ARM in DBGC1 is written to a 1.
Table 7-9. CNT Decoding Table
TBF
CNT
Description
0
000000
No data valid
0
000001
0
000010
..
..
111110
1 word valid
2 words valid
..
..
62 words valid
0
111111
63 words valid
1
000000
64 words valid; if BEGIN = 1, the
ARM bit will be cleared. A
breakpoint will be generated if
DBGBRK = 1
1
000001
64 words valid,
..
oldest data has been overwritten
..
by most recent data
111111
202
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23