MC9S12C Datasheet, PDF (358/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Module Base + 0x0004
7
R
0
W
6
5
4
3
2
1
0
CAE5
CAE4
CAE3
CAE2
CAE1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-7. PWM Center Align Enable Register (PWMCAE)
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Field
5
CAE5
4
CAE4
3
CAE3
2
CAE2
1
CAE1
0
CAE0
Table 12-8. PWMCAE Field Descriptions
Description
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
0
CAE0
0
12.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
358
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23